闊ｪ遨ｺ繝ｻ螳�ｮ咎未騾｣縺ｮ髮ｻ蟄先ｩ溷勣縺ｧ菴ｿ逕ｨ縺輔ｌ繧狗音谿翫↑繝��繧ｿ繝舌せ縲√せ繧ｿ繝ｳ繝繝ｼ繝会ｼ域ｨ呎ｺ厄ｼ峨↓縺､縺�※邏ｹ莉九＠縺ｾ縺吶�

繝帙�繝� �� 陬ｽ蜩∵橿陦楢ｳ�侭 �� HI-6138/37/36/35 謚陦楢ｧ｣隱ｬ �� BC險ｭ螳� �� BC蛻晄悄蛹匁焔鬆�

BC險ｭ螳�

BC蛻晄悄蛹匁焔鬆�

BC縺ｨ縺励※菴ｿ逕ｨ縺吶ｋ蝣ｴ蜷医↓蠢�ｦ√→縺ｪ繧句�譛溷喧謇矩��↓縺､縺�※縲∽ｸ玖ｨ倥�陦ｨ縺ｫ讎りｦ√ｒ遉ｺ縺励∪縺吶りｩｳ邏ｰ縺ｯ縺昴ｌ縺槭ｌ縺ｮ繝ｪ繝ｳ繧ｯ蜈医ｒ蜿ら�縺励※縺上□縺輔＞縲�


蜃ｦ逅�	隱ｬ譏�	髢｢騾｣繝ｬ繧ｸ繧ｹ繧ｿ縲ヽAM
繝ｪ繧ｻ繝�ヨ	繝上�繝峨え繧ｧ繧｢繝ｻ繝槭せ繧ｿ繝ｼ繝ｻ繝ｪ繧ｻ繝�ヨ	MR繝斐Φ��23逡ｪ繝斐Φ�牙�蜉�
繝ｬ繧ｸ繧ｹ繧ｿ險ｭ螳壼�譛溷喧	繝槭せ繧ｿ繝ｼ繝ｻ繧ｳ繝ｳ繝輔ぅ繧ｰ繝ｬ繝ｼ繧ｷ繝ｧ繝ｳ繝ｻ繝ｬ繧ｸ繧ｹ繧ｿ縺ｮ蛻晄悄蛹�	Master Configuration Register 1 (0x0000)
	繧ｿ繧､繝�繧ｿ繧ｰ繝ｻ繧ｫ繧ｦ繝ｳ繧ｿ繝ｻ繧ｳ繝ｳ繝輔ぅ繧ｰ繝ｬ繝ｼ繧ｷ繝ｧ繝ｳ繝ｻ繝ｬ繧ｸ繧ｹ繧ｿ	Time Tag Counter Configuration Register (0x0039)
	豎守畑繧ｭ繝･繝ｼ繝ｻ繝昴う繝ｳ繧ｿ縺ｮ蛻晄悄蛹�	Bus Controller (BC) General Purpose Queue Pointer Register (0x0038)
	繝上�繝峨え繧ｧ繧｢蜑ｲ繧願ｾｼ縺ｿ譛牙柑縲。C蜑ｲ繧願ｾｼ縺ｿ譛牙柑縲∝牡繧願ｾｼ縺ｿ蜃ｺ蜉帙Ξ繧ｸ繧ｹ繧ｿ縺ｮ蛻晄悄蛹�	繝ｻHardware Interrupt Enable Register (0x000F) 繝ｻBus Controller (BC) Interrupt Enable Register (0x0010) 繝ｻHardware Interrupt Output Enable Register (0x0013) 繝ｻBus Controller (BC) Interrupt Output Enable Register (0x0014)
BC蜻ｽ莉､繝ｪ繧ｹ繝医�蛻晄悄蛹�	BC蜻ｽ莉､繝ｪ繧ｹ繝磯幕蟋九い繝峨Ξ繧ｹ繝ｻ繝ｬ繧ｸ繧ｹ繧ｿ縺ｫ蛻晄悄繧｢繝峨Ξ繧ｹ繧偵Ο繝ｼ繝�	Start Address Register for Bus Controller (BC) Instruction List (0x0033)
BC繝｡繝�そ繝ｼ繧ｸ繝ｻ繧ｳ繝ｳ繝医Ο繝ｼ繝ｫ�上せ繝��繧ｿ繧ｹ繝ｻ繝悶Ο繝�け蛻晄悄蛹�	蜷�Γ繝�そ繝ｼ繧ｸ繝ｻ繝悶Ο繝�け縺ｫ縲√さ繝ｳ繝医Ο繝ｼ繝ｫ繝ｻ繝ｯ繝ｼ繝峨√さ繝槭Φ繝峨�繝ｯ繝ｼ繝峨√ョ繝ｼ繧ｿ繝ｻ繝悶Ο繝�け繝ｻ繝昴う繝ｳ繧ｿ縲∵ｬ｡繝｡繝�そ繝ｼ繧ｸ縺ｾ縺ｧ縺ｮ譎る俣繧貞�譛溷喧縺吶ｋ縲�	繝帙せ繝亥牡繧雁ｽ薙※SRAM 縲�0x0600��0x1FFF縲�
BC蜻ｽ莉､繝ｪ繧ｹ繝医�蛻晄悄蛹�	OP繧ｳ繝ｼ繝峨→繝代Λ繝｡繝ｼ繧ｿ縺ｮ繝壹い縺九ｉ縺ｪ繧毅C蜻ｽ莉､繝ｪ繧ｹ繝医ｒ菴懈�縺吶ｋ縲�	繝帙せ繝亥牡繧雁ｽ薙※SRAM 縲�0x0600��0x1FFF縲�
繝��繧ｿ繝ｻ繝悶Ο繝�け縺ｮ蛻晄悄蛹�	騾∽ｿ｡繝��繧ｿ繧貞性繧騾∽ｿ｡繝悶Ο繝�け繧貞�譛溷喧縺吶ｋ (RAM縺ｮ蜈ｨ縺ｦ縺ｮ蜿嶺ｿ｡繝��繧ｿ繝ｻ繝悶Ο繝�け縺ｯ縲｀R蠕後↓縺吶〒縺ｫ0x0000縺ｧ縺吶�)	繝帙せ繝亥牡繧雁ｽ薙※SRAM 縲�0x0600��0x1FFF縲�
BC螳溯｡後� 譛牙柑蛹�	繝槭せ繧ｿ繝ｼ繝ｻ繧ｳ繝ｳ繝輔ぅ繧ｰ繝ｬ繝ｼ繧ｷ繝ｧ繝ｳ繝ｻ繝ｬ繧ｸ繧ｹ繧ｿ縺ｮBCSTRT繝薙ャ繝医ｒ繧ｻ繝�ヨ縺励※BC繧呈怏蜉ｹ縺ｫ縺励∪縺�	Master Configuration Register 1 (0x0000)

HI-6138/7/6/5謚陦楢ｧ｣隱ｬ

BC險ｭ螳�

MIL-STD-1553陬ｽ蜩�

繝ｪ繝ｳ繧ｯ

繝壹�繧ｸ繝医ャ繝励∈謌ｻ繧�

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